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Static and Dynamic arrays in SV

22 Jan 2022
4 mins

An array is several memory addresses grouped. Thus, before entering the data into the array, the size of the array needs to be defined so that the compiler knows how much memory it needs to allocate. But in the case of the dynamic array the size of the array is known only during the run time. This makes it very hard for the simulator to assign continuous memory addresses. This article discusses in-depth, the static and dynamic arrays.

Static Arrays

In static arrays, the size of the array is known in the compilation time. This makes it possible for the simulator to ensure that a continuous chunk of memory is allocated for the arrays. Also, as the size is defined in the compile-time, it is not possible to change the size of the array later on during run-time. Thus these are known as static arrays.

Declaration

The size of a static array is mentioned in the declaration itself so that its size is known before compilation. Allocating memory addresses during compilation makes the simulation faster.
The declaration of a static array is the same as we have seen in the previous section.

Syntax
<datatype> [<packed_arr_size>] <identifier> [<unpacked_arr_sizes>]

<datatype> <identifier> [<unpacked_arr_sizes>]
Please note all Packed arrays are always static. This is because in a packed array continuous memory addresses are allocated by the simulator. This can only be done if the allocation is done during compile time.

Example

module static_array;
    bit [7:0] arr[4];
    bit [7:0] arr2[4];

    initial begin
        arr = '{8'd12, 8'd54, 8'd89, 8'd09};
        $display("arr = %p", arr);

        //  Only allocating one element to the array
        //  It can be seen that there is wastage of memory
        arr2[0] = 8'd23;
        $display("arr2 = %p", arr2);

        //  This is throw error as the number of elements
        //  assigned is more than the size of array
        //  arr = '{8'd12, 8'd54, 8'd89, 8'd09, 8'd123};

        //  This will also throw error as reallocation of
        //  static error is not possible
        //  arr = new [6];
    end
endmodule
Output
# arr = '{12, 54, 89, 9}
# arr2 = '{23, 0, 0, 0}
Try this code in EDA Playground

Dynamic Array

In dynamic arrays, the size of the array is known only in the run-time, which makes it difficult for the simulator to ensure that a continuous chunk of memory is allocated to the array. The size of the array can be easily changed during the run time thus giving it the name dynamic arrays.

Declaration

To declare dynamic arrays, we can just provide empty square brackets after the identifier. The size is defined either using the new[ ] keyword or the size is automatically determined from the number of elements we put in the array. The most common way is to use the new keyword as in most cases the elements of the array will not be known initially.

Syntax
<datatype> <identifier>[] = ‘{<elements of array>};

<datatype> <identifier>[];
<identifier>[] = new [<size of array>];
Please note a Packed array can not be a dynamic array. As discussed earlier packed arrays must have a continuous memory chunk which is not ensured in dynamic arrays. Also if a mixed array is declared only the unpacked part of the array can be dynamic. Thus, bit [] arr; is illegal.
bit [7:0] arr[]; is legal.

In-built methods for Dynamic Arrays

System Verilog provides two pre-defined methods for dynamic arrays. These can be used to perform operations on the array. These are:

  1. size() – to determine the size of the array. The last index will always be 1 less than the size of the array
  2. delete() – to empty the array. This also makes the size of the array as 0 as it no longer points to the previous memory chunk.

Changing the size of a dynamic array

The size of the array can anytime be changed using the new[ ] keyword. It must be noted that using the new keyword also removes all the elements of the array. This is because whenever a new keyword is used the array points to a completely new memory address and allocates the specified size.

System Verilog provides a way to preserve the data thus allowing to increase the size of the array without losing the data.

Example - arr = new[4](arr);

With the new keyword, the name of the array is also passed in parenthesis to copy the elements from the old into the new array.

Copying dynamic array

A dynamic array can be easily copied into another dynamic array using by assigning one array to another array.

Syntax

<new array> = <array to be copied>

Example

module dynamic_array;
    int arr1 [];
    int arr2 [];

    // This is show error as packed arrays
    // can not be dynamic
    // bit [] arr3;

    initial begin
        // Assigning values to the array.
        // Size is automatically determined.
        arr1 = '{12, 23, 34};
        $display("Size of arr1 = %0d", arr1.size());

        // Copying arr1 to arr2
        arr2 = arr1;

        // Array is copied. It can be verified by changing
        // a element of arr2 or arr1. The change is not
        // reflected in other array
        arr2[1] = 67;
        $display("\nChaning values\narr1 = %p", arr1);
        $display("arr2 = %p", arr2);

        arr1[0] = 56;
        $display("arr1 = %p", arr1);
        $display("arr2 = %p", arr2);

        // Changing size of arr2 while keeping the
        // old data
        arr2 = new[6](arr2);
        $display("\nChanging size\narr2 = %p", arr2);
        $display("size of arr2 = %0d", arr2.size());

        // In this the siE is changed but older
        // data is removed
        arr2 = new[4];
        $display("\nChanging size\narr2 = %p", arr2);
        $display("size of arr2 = %0d", arr2.size());

        // Deletes arr1
        arr1.delete();
        $display("\nDeleting arr1\narr1 = %p", arr1);
        $display("size of arr1 = %0d", arr1.size());
    end
endmodule
Output
# Size of arr1 = 3
#
# Chaning values
# arr1 = '{12, 23, 34}
# arr2 = '{12, 67, 34}
# arr1 = '{56, 23, 34}
# arr2 = '{12, 67, 34}
#
# Changing size
# arr2 = '{12, 67, 34, 0, 0, 0}
# size of arr2 = 6
#
# Changing size
# arr2 = '{0, 0, 0, 0}
# size of arr2 = 4
#
# Deleting arr1
# arr1 = '{}
# size of arr1 = 0
Try this code in EDA Playground

Static Vs Dynamic

StaticDynamic
1. In static arrays the size of the array is fixed during the entire simulation.1. The Size of the dynamic array can be changed during the simulation.
2. There is lot of wastage of memory as the size of array is considered keeping in mind the maximum possible elements that can be stored. It is not necessary that we use all the location in simulation.2. As the size can be changed dynamically thus there is no wastage of memory.
3. It is faster as the memory allocation is done during compile time.3. It may not be efficient as memory allocation is done during the run-time and the size can change during simulation. Also it is not guaranteed that continous memory block will be allocated slowing the access to array.
4. Can be used to declare both packed and unpacked arrays.4. Can be used to declare only unpacked arrays.

Thus, the dynamic array is introduced in System Verilog to overcome some of the limitations of the static array as metioned above.