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Interface in SV
23 Dec 2022
In Verilog, we are used to defining ports while writing the modules. These ports act as the connection between different modules or between the design and the test bench. Defining ports and maintaining connections becomes a lot more difficult when the number of signals inside a port is very high. In…
Events in System Verilog
19 Sep 2022
Events or named events are static objects like what we have seen in Verilog. In System Verilog, basic operation of events remains the same as that of the Verilog, but some enhancements are done in System Verilog. In this article we will learn more about the events in detail. What are events? Events…
Semaphores in System Verilog
31 Jul 2022
We have seen that in System Verilog various processes can run in parallel. This can create a problem if 2 processes access some variables. Semaphore provides a solution to this problem. Let’s understand the use of semaphores in detail in this article. Why are semaphores needed?? Let us consider a…
Mailboxes in System Verilog
22 Jul 2022
Using fork-join we can create multiple processes which run in parallel. These processes need some mechanism to communicate with each other or share the resources properly. Thus, in System Verilog inter-process communication mechanisms such as mailbox and semaphore were introduced. In this article…
Multiple process in system verilog
17 Jul 2022
In Verilog, fork-join construct is used to create a new thread which can run in parallel to code defined in another block. In System Verilog, a few additions were made to give more flexibility in the way we can create a new process. Also, a new process class is introduced in System Verilog which can…
Procedural blocks in system verilog
16 Jul 2022
In Verilog, there are initial and always procedural blocks as we have seen. In system Verilog, these procedural blocks were improved, and a few more procedural blocks were added. Some of these added procedural blocks are synthesizable and some are non-synthesizable. In this article we will see these…