# Verilog Operators

##### 6 mins

Operators are important in any programming languages as they help to perform various arithmetic, logical and comparison operations. Operators always acts upon some constants or variable which is known as operands. In general, the operators can be divided into 3 categories based on the number of operands a operators need.

1. Unary Operator – It has only one operand. Ex- `~`, `!` are unary operators.
2. Binary Operators – It has 2 operands. Ex - `+`, `*`, etc are binary operators.
3. Ternary Operator – It has 3 operands. Ex - `?:` is ternary operator.

In Verilog, there are some unique operators which is present due to the 4 state variables. In Verilog, the operators can be divided into 6 groups namely:

1. Arithmetic Operators
2. Logical Operator
3. Bit Wise Operator
4. Comparison Operator
5. Reduction Operator
6. Shift Operator

### Arithmetic Operators

Arithmetic operators are used to perform some arithmetic operations on the operands. They are mostly Binary in nature, i.e., have 2 operands. Some of the common arithmetic operators are:

• `+` - This is used for binary addition of 2 operands. It can also be used as a unary operator to indicate the sign of the operand. Ex - `c = a + b` or `d = +4’b23`
• `-` - This is used for binary subtractions of 2 operands. It can also be used as unary operator to indicate -ve sign in the operand. Ex - `c = a – b` or `c = -4’b23`
• `*` - This is used to multiply 2 operands.
• `\` - This is used to divide the 1st operand with the 2nd operand.
• `%` - This gives the remainder of the division operation.

In Verilog, `++` and `--` operators, i.e., incremental arithmetic operators are not valid. Instead, `c = c1` can be used for repeated increments.

#### Example

In the below example, some points need to be noted. In highlighted line 3, another variable `mul_res` to store multiplication result is declared. This is done because, the result of multiplication is usually large and it would not fit in the original width of the operands. Thus, the result should have more width, usually, twice the width of the operand.
Result of division may lead to fractional number, thus a `div_res` of real data type is also declared in line 5, to store division result. If we store the result in normal reg or integer variable, the result will be rounded off as in line 21. Also, if both the operands are integer or reg, the result will always be in integer, i.e., rounded off value even if the result is stored in real data type as seen in highlighted line 24. Thus, to get real number as output any one of the operand should also be a real number as in highlighted line 25.

``````module arithmetic_operators;
reg signed [4:0] a, b, res;
reg signed [6:0] mul_res;
real a1;
real div_res;

initial begin
a = 5'd5;
b = 5'd9;
a1 = 5;

res = a + b;
\$display("%0d + %0d = %0d", a, b, res);

res = a - b;
\$display("%0d - %0d = %0d", a, b, res);

mul_res = a * b;
\$display("%0d * %0d = %0d", a, b, mul_res);

res = a / b;
\$display("%0d / %0d = %0d (in integer)", a, b, res);

div_res = a / b; // This will output integer value as both the operands are integer
div_res = a1 / b; // This will output real value as one of the operands (a1 is real)
\$display("%0d / %0d = %f (in real)", a, b, div_res);
\$display("%0d / %0d = %f (in real)", a1, b, div_res);

res = b % a;
\$display("%0d %% %0d = %0d", b, a, res);
end
endmodule``````
##### Output
``````# 5 + 9 = 14
# 5 - 9 = -4
# 5 * 9 = 45
# 5 / 9 = 0 (in integer)
# 5 / 9 = 0.000000 (in real)
# 5 / 9 = 0.555556 (in real)
# 9 % 5 = 4``````
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### Logical Operators

Logical Operators are used to combine 2 expressions together. Depending on the result of the expression, the logical operator will give the output. The output of the logical operator will always be a binary value, i.e., logical true or false.

• `&&` - Also known as logical AND. It will output 1 or logical true only when both the expressions (operands) are true.
• `||` - Also known as logical OR. It will output 1 or logical true even if any one of the expressions (operands) is true.
• `!` - Also known as logical NOT. This is a unary operator and will output 1 or logical true if the expression (operand) is false.

Please note in case the operands are not a conditional expression, i.e., if it is a variable or constant, then any value greater than 1 is considered as true and the output is evaluated on that basis. If any one of the operands in `X`, then the o/p is also `X` for all operators.

### Bit-wise Operators:

Bit-wise operators are mostly binary in nature, i.e., it will have two operands. These operands perform operations bit wise, i.e., it will take one bit from both the operands and calculate one bit of the result. This will be done for all the bits present in the operand.

• `&` - Bitwise AND – This will perform and operation on the bits of the operands. `c = 2’b10 & 2’b11` will evaluate to `c = 2’b10` as `1 & 1 = 1; 1 & 0 = 0`. One of the most common use of this operand is to make some value according to some pattern.
• `|` - Bitwise OR – This will perform OR operation on the bits of the operands. `c = 2’b10 | 2’b11` will evaluate to`c = 2’b11`as`1 | 1 = 1; 1 | 0 = 1`.
• `~`- Bitwise NOT – This a unary operator and will inverse the bits of the operand. Thus, the result will be 1’s complement of the operand.
• `^` - Bitwise XOR – This performs XOR operation on the bits of the operand. `c = 2’b10 ^ 2’b11` will evaluate to`c = 2’b01`as`1 ^1 = 0; 1 ^ 0 = 1`.
• `~^` or `^~` - Bitwise XNOR – This performs XNOR operation on the bits of the operand. `c = 2’b10 ~^ 2’b11` will evaluate to`c = 2’b10`as`1 ~^ 1 = 1; 1 ~^ 0 = 0`.

### Comparison Operator

These operators are mainly binary in nature having 2 operands. These will compare the operand and give the output as logical `1` or `0`, i.e., true, or false.

OperatorDescription
>=Greater than and equal to
<=Smaller than and equal to
>Greater than
<Smaller than
==Equal to
!=Not Equal to

#### Special Comparison Operators

There are some special comparision operators in Verilog for comparision of 4 state variables.

• `===` This is a special operator in Verilog which is equivalence operator for 4 state variables. In `==` the `X` and `Z` states are not compared, and the output is `X` if `X` or `Z` is present in the operands, but `===` will also consider `X` and `Z` state while comparison and the output will always be 1 or 0.
• `!==` — This is the same as `===` but it checks for not equal to.
##### Example

In the below example the output of the line 6 will be `x` as the operands contains `x` and `z`, whereas the output of line 7 will be `1` as `===` compares all the states.

``````reg [3:0] a, b;
initial begin
a = 4'bx01z;
b = 4'bx01z;

\$display("a == b is %b", a==b); // Output is x
\$display("a === b is %b", a===b); // Output is 1
end``````

### Reduction Operator

These operators are unary in nature, i.e., have only one operand. It reduces a multiple bit operand into a single bit based on the operator.

• `&` - Reduces the operand by taking the AND of each bit present in the operand. Ex – `c = &4’b1100` evaluates to `c = 1’b0` as `1’b1 & 1’b1 & 1’b0 & 1’b0` is 0
• `|` - Reduces the operand by taking the OR of each bit present in the operand. Ex – `c = |4’b1100` evaluates to `c = 1’b1` as `1’b1 | 1’b1 | 1’b0 | 1’b0` is 1
• `^` - Reduces the operand by taking the XOR of each bit present in the operand. Ex - `c = ^4’b1100` evaluates to `c = 1’b0`.
``````module reduction_operators;
reg [3:0] a;
initial begin
a = 4'b1011;
\$display("&a = %b", &a);
\$display("|a = %b", |a);
\$display("^a = %b", ^a);
\$display("~&a = %b", ~&a);
\$display("~|a = %b", ~|a);
\$display("~^a = %b", ~^a);
end
endmodule``````
##### Output
``````# &a = 0
# |a = 1
# ^a = 1
# ~&a = 1
# ~|a = 0
# ~^a = 0``````

### Shift Operator

Shift Operator are of 2 types:

1. Logical shift operator – This shifts the bits of the operand to either left or right.
2. Arithmetic Operator – Arithmetic shift operator respects the sign of the operand, if the operand is of signed data type, then the left or the right place is filled with the value of the sign bit, i.e., MSB. If the operand is of the unsigned data type, then the output is same as that of the logical shift operator.
``````module operators;
reg [4:0] a;
reg signed [4:0] b, c;

initial begin
a = 5'b10100;
b = 5'b10100;

// Shift operation
\$display("original value of a: %b", a);
\$display("original value of b: %b", b);

c = b << 2;
\$display("b after logical left shifting- %b", c);
c = b <<< 2;
\$display("b after arithmetic left shifting- %b", c);

c = a <<< 2;
\$display("a after arithmetic right shifting- %b", c);

c = b >> 2;
\$display("\nb after logical right shifting- %b", c);
c = b >>> 2;
\$display("b after arithmetic right shifting- %b", c);

// as 'a' is an unsigned variable thus the output will be same as the logical shift operator
c = a >>> 2;
\$display("a after arithmetic right shifting- %b", c);
end
endmodule``````
##### Output
``````# original value of a: 10100
# original value of b: 10100
# b after logical left shifting- 10000
# b after arithmetic left shifting- 10000
# a after arithmetic right shifting- 10000
#
# b after logical right shifting- 00101
# b after arithmetic right shifting- 11101
# a after arithmetic right shifting- 00101 ``````
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### Some Other operators

#### Bit-select Operator

This operator is used to select single bit or multiple bits from a variable. `[]` is the bit select operator. Ex – `a[3:1]` will select the bits from position 1 to 3. Read more about arrays and bit selection in this article.

#### Concatenation Operator

This operator is used to concatenate 2 or more variables or nets into a single variable or net. `{}` is the concatenation operator and each variable or net is separates using `,`. Ex - `a = {2’b10, 2’b11}` will evaluate to `a = 4’b1011`.

#### Replication Operator

This operator replicates a given number or a variable for a specified number of times. `{{}}` is known as the replication operator. Basic syntax is `{n{m}}`, the number `m` will be replicated `n` number of times. It must be noted that `n` must always be a constant or a parameter, otherwise there can be compile time error. Ex - `a = {3{2’b10}}` will evaluate to `a=6’b101010`, i.e., the number 10 will be repeated 3 times.

#### Example

``````module special_operators;
reg [3:0] a;
reg [5:0] b;
reg [1:0] n, m;
initial begin
n = 3;
m = 2'b10;

\$display("Concatenation operator");
// operands can be a constant or a variable
a = {2'b10, 2'b11};
\$display("a = %b", a);
a = {m, 2'b11};
\$display("a = %b", a);

\$display("\nReplication Operator");
// m can be a constant or a variable; n must be a constant
b = {3{2'b10}};
\$display("b = %b", b);
b = {3{m}};
\$display("b = %b", b);

// b = {n{2'b10}};  // This will show error

\$display("\nBit-select Operator");
a = b[4:1];
\$display("a = %b", a);
end
endmodule``````
##### Output
``````# Concatenation operator
# a = 1011
# a = 1011
#
# Replication Operator
# b = 101010
# b = 101010
#
# Bit-select Operator
# a = 0101``````
Try this code in EDA Playground