Data Types in Verilog
Data types represents the type of data a variable can hold. Some of the reader who are familiar with other languages like C, would know that the variables can store any data which can be represented in binary, i.e., 1 or 0. Thus only states are present for any data types. But in hardware domain, the things are slightly different. Apart from 0 and 1, we can have other states also. Suppose if we are using a wire and one end of the wire is not connected or temporarily disconnected, or for flip-flops have some intermediate states in which the state is non determinate. Thus, we see that to accurately represent hardware, we need to have some more states in a variable. In Verilog, data types are designed in a way that it can represent the bits stored in Flip Flop or the wire which connects b/w logic gates.
As discussed earlier, there is a need for states other than 0 or 1 to represent hardware. Thus, in Verilog, we have variables having 4 states.
- 0 – Represents the logic 0
- 1 – Represents the logic 1
- X – Represents the don’t care state, i.e., the non-determinate state of flip flops.
- Z – Represents high impedance, i.e., disconnected wires.
Every Verilog data type can hold any value amongst these 4 states.
In waveforms, all the 4 states are represented using different colour coding. Don’t care is usually represented using red,
z is represented using blue, and
1 is represented using green. Please note that there can be slight variations in the colour coding from simulator to simulator.
Verilog offers a wide variety of data types that are highly relatable to real-life hardware. The list of variables are:
Lets see about the different data types in detail
reg represents a single bit storing element in a real hardware. Thus, reg are sequential elements and it can hold the data until, it is changed. During synthesis it is synthesised into a flip-flop.
wire represents a real-life wire in hardware and is used to connect 2 logic elements or modules. It cannot hold data just as the case in real life wire.
integer is a 32-bit signed variable. It similar to
reg [31:0] except the fact that integer is a signed variable and thus store negative values.
real is a double precision floating variable. It can be used to store decimal values if required.
time is a 64-bit variable which is used to store the simulation time. It cannot hold decimal values thus the time is rounded off to integer.
realtime is just like time, but it can store decimal values also.
In Verilog, there is no special data types for string. Strings are stored in
reg data type only.
Each character in a string is stored in ASCII format, and have a size of 8-bits. Thus, to store a string of 5 characters we need
8*5 = 40 bits.
module xyz; reg [(8*5)-1:0] str; initial begin str = "Hello"; $display("str = %s", str); end endmodule
There are some other data types also, which are used for special purpose.
parameter is a run time constant for storing integers, real numbers, time, delays, or strings. The values are defined during the compile time only and it cannot be changed during the run time. The value of the parameter can be changed during the compile time using
These are generally used for making a configurable module, i.e., module whose parameter can be changed during compile time.
This is a same as
parameter but its scope is limited to the module in which it is declared. Scope means the part of code from which it can be accessed. Thus,
localparam cannot be accessed globally and is limited to a block.
event is used to declare a variable which can be used to synchronize different blocks. The events can be triggered using
module xyz; event event_name; // This block will trigger the event at 50 time units initial begin #50; -> event_name; end // This block will only execute when event_name is triggered always @event_name begin $display("event has been triggered at time = %0t", $time); end endmodule