Delays in Verilog
In our introductory article we saw that Verilog is an HDL simulation language and the simulation happens in the timescale which is provided in the code. Also, there are special delay operators in Verilog which can be used to provide in the simulation. In this article we learn more about these delays and why it is needed. We will focus more on the deign side in this article.
We have already discussed how delays are used in a testbench and hence, in this article we will discuss the use of delay in design part. In test bench, delays are used to synchronize signals, components or generate stimulus at a specific event.
But delays are also used in the design to simulate the path and gate delays seen in real-life circuit. If in simulation we do not consider these factors, it can lead to setup or hold violations in silicon rendering the chip useless.
We must understand here that delay operator used in design are just for simulation and it will not be synthesized in actual hardware. Thus, delay operators have no effect on final netlist.
Path delay is delay between two nodes of a circuit. In silicon, gates, or flops (nodes) will be connected through wire. The scale of design is exceedingly small usually in nanometres or micrometres and there would be lot of parallel wires in the silicon. Due to this, lot of parasitic RCs are seen in silicon. This can lead to the delay in the signal.
In Verilog, this delay is represented by using the delay operator before assignment statement.
#30 a => b;
Gate delays are due to the intrinsic nature of transistor used to design gate. Transistor can have parasitic RCs present between the drain, source, and gate. This affects the switching time of transistor and the Toff (fall) and Ton (rise) time of the gates. Thus, there is some delay in propagation of output from the actual input time. This delay is also known as propagation delay.
In Verilog, this delay can be represented by using delay operator just after the assignment operator.
a => #30 b;
Once the RTL is synthesized and netlist are created, all the logic gets replaced with actual nets and gates/flops. In this stage, it is crucial to have a delay-based simulation on netlist to verify that the design is working with expected delays.
Gate delays are derived from the cell library used for synthesis. All cell libraries have a functional model which has gate delays defined for different gates.
Path delays are derived from the PnR (place and route) stage of the design cycle. In this stage, the cells are placed and specialized tool is used to extract RC details from the nets.
Setup and hold violation are usually captured in STA (Static timing analysis) of the design cycle. But the delay-based simulation is also used to verify for any violation. This is known as dynamic timing analysis because there is input stimulus to the circuit which will change in the simulation. Let us understand these violations and what affect it have on the chip.
Setup violation happens when the data path is slower than the clock path. Data path usually have a lot of gates in the path which can cause the overall delay in data path to be more than clock path. When this happens, clock will arrive earlier in a flop and flop will capture wrong data as data will take some more time to arrive.
If this violation is not captured in the design phase, then in silicon we need to decrease the clock speed to remove these violations. Reducing clock speed decreases the chip performance and thus not an ideal situation.
Some fixes for setup violation
- Reduce buffers in the data path as this slows down the data path.
- Relace a buffer with two inverters. Inverters have less than half of the delay of buffers.
- Use repeaters in longer route to reduce parasitic RCs. There are lot more ways to fix setup violation which are out of scope of this article.
Hold violation happens when data path is faster than the clock path. This means that the data will not be stable when flip flop samples the data and thus hold violation will happen.
If this violation is not captured in the design phase, then there is no way to remove these violations in chip and chip is useless. In simple terms ‘JUST DUMP THE CHIP’.
Some fixes for hold violation.
Hold violations are easy to fix in design phase.
- Add buffer in data path to increase delay.
- Decrease cell size which will decrease drive load of the cell, ultimately increasing delay. Thus, we see that it is very crucial to identify these violations in design phase and use appropriate measures to solve them in design phase itself.
Setup and hold violation can be solved in numerous ways in the design phase. Having detailed discussion on the solutions is out of the scope of this article. Some of the solutions are mentioned above in respective violation section.
In this article, we saw how the delay-based simulation crucial role in identifying violations which can render the chip useless. Though delay operator does not play a direct role in the RTL design but is important in terms of simulation.